The market is calling; it’s time to put fan-out wafer level packaging (FOWLP) on your roadmap. Conventional FOWLP is hampered by cost of capital, die-attach cost and yield. M-Series™ was built from the ground up to break down those barriers to adoption.
Built on Deca’s Autoline, M-Series breaks through the capital cost barrier. Lower precision, lower cost and fast die-placement tools address die-attach cost, and Deca’s proprietary Adaptive Patterning™ technology adjusts for die-shift variations on the fly to achieve 99.9% yield. This rugged, fully encapsulated FOWLP technology provides high reliability, ideally suited for mobile applications.
M-Series gives you:
- Improved board-level reliability
- Size reduction for single- and multi-die projects
- Adaptive patterning for advanced silicon nodes
- Fine line and space routing
- High-speed pick-and-place
- Substrate elimination
There is FOWLP, and then there is M-Series.
M-SERIES™ FOWLP: A Beginner’s Guide
Deca’s M-Series™ FOWLP is a rugged, fully molded fan-out, wafer-level chip-scale package (WLCSP) technology that provides high reliability ideally suited for mobile applications. M-Series features Adaptive Patterning™, a dynamic design and patterning process that resolves the issues associated with shifting die within an embedded device structure.
What is Fan-out Wafer-Level Technology?
Fan-out wafer-level technology is the process of embedding singulated die from a silicon wafer in molding compound to create a reconstituted wafer. Interconnect traces are “fanned out” through a redistribution layer (RDL) to solder bumps to achieve higher I/O density and flexible integration.