Semiconductor Engineering – Planning For Panel-Level Fan-Out
Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging.
Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes.
Fan-out packaging on a large square panel is significantly more difficult, and mass adoption is not expected anytime soon. Still, one of the problems with all advanced packaging is the cost, and companies such as ASE, Powertech, Nepes, and Samsung are looking to panel-level packaging to provide economies of scale. A panel processes more packages than a round wafer, which reduces the cost. For example, a 300mm wafer can process 2,500 6mm x 6mm packages, but a 600mm x 600mm panel can accommodate 12,000 packages, according to ASE.